1. Field of the Invention
The present invention relates to a single-chip microcomputer including an erasable and electrically-programmable read-only memory.
2. Background Art
FIG. 1 shows a block diagram of the circuitry for reading from and writing into an electrically-programmable read-only memory included in a conventional single-chip 8-bit microcomputer. The dotted line, chain line and full line in FIG. 1 respectively show the flow of electric power, control signals and data signals. FIG. 1 also shows external power supplies V.sub.cc and V.sub.pp, control signals PGM (relating to program memory), CE (relating to chip enabling) and OE (relating to output enabling), which are externally applied. This figure also shows 13-bit address signals AD.sub.0 -AD.sub.12 and 8-bit data signals D.sub.0 -D.sub.7. A writing control circuit 2 receives the control signals PGM, CE and OE from the outside, and sends a control signal PRG* to a writing circuit 3 and to a power supply switchover circuit 4. A reading control circuit 5 also receives the control signals PGM, CE and OE from the outside and sends reading signals .phi..sub.R and RP to a reading circuit 6. A Y-directional decoder (column decoder) 7 decodes the address signals AD.sub.1 -AD.sub.4, and sends decoded signals y.sub.i to a Y-directional selector 8. An X-directional decoder (row decoder) 9 decodes the address signals AD.sub.5 -AD.sub.12, and sends decoded signals x.sub.i to the memory cells 10 of the EPROM. The address signals and the data signals are inputted and outputted through I/O (input/output) ports 11a, 11b and 11c. The address signals AD.sub.0 -AD.sub.12, which are inputted through the I/O ports 11a and 11b and are 13 bits wide, are transmitted through an address bus so that the address signal AD.sub.0 is entered into the writing circuit 3, the address signals AD.sub.1 -AD.sub.4 are entered into the Y-directional decoder 7, and the address signals AD.sub.5 -AD.sub.12 are entered into the X-directional decoder 9. The data signals, which are inputted and outputted through the I/O port 11c, are transmitted through a data bus so that the data signals D.sub.0 -D.sub.7 are entered into the writing circuit 3 or sent out from the reading circuit 6.
FIG. 2 shows a circuit diagram illustrating the structure and connections of the writing control circuit 2 shown in FIG. 1. The same reference symbols denote the same portions in FIGS. 1 and 2. The writing control circuit 2 in FIG. 2 includes an inverter 21, a NAND gate 22 and a NOR gate 23.
Since reading from the EPROM shown in FIG. 1 is performed in the same manner as that of a conventional ROM or RAM, the description of the reading from the EPROM is omitted herein and only writing into the EPROM is described. To write into the EPROM, the single-chip microcomputer is reset and the power V.sub.pp, which is a voltage of 21 V, is applied. At that time, the other power V.sub.cc is a voltage of 5 V, the control signal PGM is set to a low level L, CE is set to a high level `H` and OE is set at a low level `L`. The address signals AD.sub.0 -AD.sub.12 are inputted through the I/O ports 11a and 11b and the data signals D.sub.0 -D.sub.7 are inputted through the I/O port 11c. The output from the NAND gate 22 and the signal PRG* are at a high level `H` and a low level `L`, respectively. When the signal PGM is thereafter set at a high level `H` , the signal PRG* of a high level `H` is applied to the writing circuit 3 so that a data signal whose logic state is `0` or `1` is written into a memory cell 10 selected by the decoded address.
The control signal OE being at a high level `H` means that the data signals are entered from the I/O port 11c into a writing circuit 3 through the data bus. The address signals are always inputted from the I/O ports 11a and 11b. Namely, the address signals AD.sub.1 -AD.sub.4 are entered into the Y-directional decoder 7, and the address signals AD.sub.5 -AD.sub.12 are entered into the X-directional decoder 9.
When the control signal PRG* is set at a high level `H`, the output V.sub.cc /V.sub.pp from the power supply switchover circuit 4 becomes the higher power voltage V.sub.pp so that a voltage of 21 V is applied to the Y-directional decoder 7 and the X-directional decoder 9. Therein, the voltage of the decoded signals y.sub.i and x.sub.i take the same level as the high-level power V.sub.pp.
If the logic level of a data bit is `0` in the writing circuit 3 when the signal PRG* is at a high level `H`, the voltage V.sub.pp is applied to the Y-directional selector 8 through a signal line 13. If the logic level of the data bit is `1` in the writing circuit 3, the signal line 13 is disconnected. For that reason, when the logic level of a written data signal is `0`, a voltage of the same level as the power voltage V.sub.pp is applied from the writing circuit 3 through the Y-directional selector 8 to the drain of the transistor of a memory cell selected by an address signal AD.sub.1 -AD.sub.12. Also, a voltage of the same level as the power voltage V.sub.pp is applied from the X-directional decoder 9 to the gate of the transistor of the memory cell 10, and electrons enter into the floating gate of the transistor of the memory cell. When the logic level of written data signal is `1`, the entry of the electrons into the floating gate does not take place because no high voltage is applied to the drain of the transistor. The electrons entered into the floating gate are not spontaneously discharged, but are retained. The logic of a signal stored in the transistor of the memory can be read in terms of whether or not the threshold potential has been changed due to the entry of the electrons into the floating gate.
In a conventional single-chip microcomputer including the EPROM, writing into the EPROM cannot be performed without entering the address signal and the data signal by an external device such as an EPROM writer when the microcomputer is out of operation. Therefore, the conventional microcomputer has a problem that a simple operation process which causes the microcomputer to execute its own writing instruction so as to write into the EPROM so as to write into a RAM cannot be performed.